/**
 ******************************************************************************
 * @file    LwIP/LwIP_HTTP_Server_Raw/Inc/stm32f4xx_hal_conf.h
 * @author  MCD Application Team
 * @version V1.2.1
 * @date    13-March-2015
 * @brief   HAL configuration file.
 ******************************************************************************
 * @attention
 *
 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of STMicroelectronics nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_ETH_CONF_H
#define __STM32F4xx_ETH_CONF_H

#ifdef __cplusplus
extern "C" {
#endif

#define _eth_delay_    Delay   /* User can provide more timing precise _eth_delay_ function */

/* Definition of the Ethernet driver buffers size and count */
#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
#define ETH_RXBUFNB                    ((uint32_t)5)       /* 5 Rx buffers of size ETH_RX_BUF_SIZE  */
#define ETH_TXBUFNB                    ((uint32_t)5)       /* 5 Tx buffers of size ETH_TX_BUF_SIZE  */

/* Delay when writing to Ethernet registers*/
#define PHY_RESET_DELAY    	((uint32_t)0x0000FF)
#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
#define PHY_CONFIG_DELAY    ((uint32_t)0x00000FFF)

/* PHY Address*/
#define ETH_PHY_ADDRESS		             0x01
/* PHY Configuration delay */

#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)

/* Section 3: Common PHY Registers */

#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */

#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */

#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */

#define PHY_BCR_AUTONEG_ENABLED			((uint16_t)0x1000)	/*!< PHY Autoneg */
#define PHY_BSR_AUTONEG_COMPLETE		((uint16_t)0x20)

#define PHY_SR							((uint16_t)0x0001) /* PHY status */
#define PHY_CONTROL_REG					((uint16_t)0x001F) /* PHY control */
#define PHY_USED_100BASE_FULL_DUPLEX	((uint16_t)0x0018) /* PHY Speed  */
#define PHY_USED_100BASE_HALF_DUPLEX	((uint16_t)0x0008) /* PHY Speed  */
#define PHY_USED_10BASE_FULL_DUPLEX		((uint16_t)0x0014) /* PHY Speed  */
#define PHY_USED_10BASE_HALF_DUPLEX		((uint16_t)0x0004) /* PHY Speed  */
#define PHBSROL_AUTONEG_COMPITE			((uint16_t)0x2080)
// interrupt
#define PHY_INTERRUPT_REG				((uint16_t)0x1B) /* Interrupt Control Register */
#define PHY_INTERRUPT_EN_LINK_DOWN		((uint16_t)0x00400)
#define PHY_INTERRUPT_EN_LINK_UP      	((uint16_t)0x00100)
#define PHY_INTERRUPT_LINK_UP			((uint16_t)0x01)
#define PHY_INTERRUPT_LINK_DOWN			((uint16_t)0x04)

#ifdef __cplusplus
}
#endif

#endif /* __STM32F4xx_HAL_CONF_H */


/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
